The miniaturization of electrical components and their integration on a single piece of semiconductor material has been the catalyst for a world wide information revolution. As integrated circuit technology has progressed, it has been possible to store increasing amounts of digital data in a smaller space at less expense and still access the data randomly, quickly and reliably. Central to this increased ability to store and retrieve data has been the dynamic random access memory, or DRAM fabricated as an integrated circuit.
In the case of mass produced DRAMs, the cost per bit of memory has historically decreased as the number of bits which can be reliably stored on each integrated circuit has increased. Thus, it is advantageous to pack as many bit-storing memory cells as possible on each square unit of planar surface area available on a semiconductor integrated circuit.
DRAMs are formed of a large number of storage nodes which require transistors and capacitors in order to store information. The state of the art of fabricating the storage nodes of DRAM circuits has progressed to the point where the transistors of the nodes can be made much smaller than the capacitors.
In order to function properly within the nodes, the capacitors must possess a minimum amount of capacitance. If a capacitor exhibits too little capacitance, it loses the charge placed upon it too rapidly, causing errors in data storage. Thus, it is essential that the electrodes of storage node capacitors be large enough to retain an adequate charge in spite of parasitic capacitances and noise that may be present during circuit operation. Generally, it is desirable that each memory cell capacitor have as much capacitance as possible, but at least 20.times.10.sup.-15 farads, and preferably more than 60.times.10.sup.-15 farads of charge storage capacity.
The capacitance value, C, of a capacitor is dependent upon the dielectric constant, .epsilon., of the material placed between the electrodes of the capacitor, the distance, d, between the electrodes, and the effective surface area, A, of the electrodes. The relationship may be expressed C=A.epsilon./d. In many cases the material used as the dielectric between the electrodes of the capacitor is limited to only a few possibilities. The thickness of the dielectric is limited by leakage current. Thus, the parameter which can most easily be varied to obtain increased storage capacity in DRAM capacitors is the surface area of the capacitor electrodes.
Therefore, it is a goal of DRAM designers to increase the surface area of capacitor electrodes as much as possible. It is also a goal to reduce the planar area occupied by each capacitor to a minimum so that as many memory cells as possible can be packed onto a single integrated circuit. Various three dimensional structures have been proposed and adopted in the art of DRAM fabrication to maintain the value of capacitors at a high level while keeping the planar area, or footprint, allocated to the capacitor at a minimum.
Among the proposed methods for maintaining cell capacitance while decreasing the planar area devoted to the cell capacitor is a "trench transistor cell" such as that described in Lu, "Advanced Structures for Dynamic RAMs", IEEE Circuits and Devices Magazine, pp. 27-35, (January 1989). In the trench transistor cell of the Lu paper, the capacitor cell is a vertical structure with an access transistor which is also vertica. The access transistor is placed above the cell capacitor. The described trench cell provides greater capacitor electrode area in a small planar area when compared to many planar capacitor structures. However, it provides only a modest increase in charge storage capacity, as well as additional difficulties during fabrication.
It is well known in the art that the storage capacitance of a node capacitor can be enhanced without increasing either the area required for the cell or the storage electrode height by "roughening" the silicon used to form a storage node electrode. In this method, a relatively flat silicon layer is subjected to surface migration and grain growth until the silicon layer forms into rounded clusters. An increase in capacitance results because the surface area of the rounded silicon clusters is greater than that of a relatively flat silicon layer. The process of roughening the silicon used to form a storage node electrode has been applied in the context of container capacitors to roughen both the inner and outer surfaces of the container capacitor. However, these known methods for roughening both the inner and outer electrode surfaces of a container capacitor electrode either require costly process steps, or result in capacitor electrode having a planar surface area that is undesirably large.
One known method for roughening both the inner and outer electrode surfaces of a container capacitor requires forming the container capacitor electrode from amorphous polysilicon, seeding the surfaces of the amorphous polysilicon electrode with a hydride such as, for example, SiH.sub.4 or Si.sub.2 H.sub.6, and annealing the seeded structure at approximately 700.degree. C. and 10.sup.-8 torr for a period of about 20 seconds. Although the annealing step causes both the inner and outer surfaces of the container capacitor electrode to roughen, the temperature and pressure required for the annealing step render this process costly from a manufacturing standpoint and therefore undesirable.
Another known method for roughening both the inner and outer electrode surfaces of a container capacitor requires forming an internal container capacitor structure from smooth polysilicon, and then depositing a layer of rough polysilicon over top of the smooth polysilicon structure. In this method, the minimum thickness of the internal smooth polysilicon is believed to be about 500 angstroms, and the minimum thickness of the rough polysilicon lying on top of the smooth polysilicon is believed to be about 500 angstroms. Since the rough polysilicon is deposited on top of the smooth polysilicon both on the inner and outer surfaces of the container capacitor electrode, the minimum width of a container capacitor electrode formed in accordance with this method is believed to be approximately 1500 angstroms. Since it is a goal of DRAM designers to decrease the planar surface area occupied by each capacitor on an integrated circuit, it would be desirable to have a container capacitor electrode with roughened inner and outer surfaces having a thickness that is substantially less than 1500 angstroms.
It is therefore an object of the present invention to provide a container capacitor structure for use on an integrated circuit, wherein both the inner and outer surfaces of the container capacitor electrode are roughed.
It is a further object of the present invention to provide a container capacitor structure for use on an integrated circuit, wherein the thickness between the inner and outer surfaces of the container capacitor electrode is substantially less than 1500 angstroms.
It is a still further object of the present invention to provide a method for forming a container capacitor structure for use on an integrated circuit, wherein the step of annealing the capacitor structure at a high temperature is not required to form the capacitor structure.
It is another object of the present invention to provide an integrated circuit capacitor structure and method for forming such an integrated circuit capacitor structure which can be reliably manufactured and operated.
It is another object of the present invention to provide an integrated circuit capacitor structure and a method for forming such an integrated circuit capacitor structure which is particularly adapted for integration into DRAM integrated circuits.
These and other objects and advantages of the invention will become more fully apparent from the description and claims which follow or may be learned by the practice of the invention.